Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclosure via physical access.
2020-03-12T21:15:14.373
2024-11-21T04:53:47.337
Modified
CVSSv3.1: 5.9 (MEDIUM)
AV:L/AC:L/Au:N/C:P/I:P/A:N
3.9
4.9
Type | Vendor | Product | Version/Range | Vulnerable? |
---|---|---|---|---|
Operating System | intel | max_10_fpga_firmware | * | Yes |
Hardware | intel | max_10_fpga | - | No |